50 Gbit/s real-time test environment for integrated photonic DQPSK receivers

Abstract. In this paper an FPGA-based test system for high-speed transmission experiments with integrated photonic receivers is presented. Pseudorandom binary sequences are generated inside the FPGA and encoded as either differential quadrature phase shift keying (DQPSK) or quadrature phase shift keying (QPSK) signals. The DQPSK encoder uses a 64-fold parallel-prefix-layers architecture for real-time operation which allows for a maximum internal encoder data rate of 64 Gbit/s. Two-fold parallel data streams of I and Q signals suitable for driving an optical IQ-modulator can be transmitted and received by four 12.5 Gbit/s transceivers. Integrated bit error testers are used to determine bit error rates in real-time.