Recently, nonlinear amplifiers based on the supercritical Andronov–Hopf bifurcation have become a focus of attention, especially in the modeling of the mammalian hearing organ. In general, to gain deeper insights in the input-output behavior, the analysis of bifurcation based amplifiers requires a flexible framework to exchange equations and adjust certain parameters. A DSP implementation is presented which is capable to analyze various amplifier systems. Amplifiers based on the Andronov–Hopf and Neimark–Sacker bifurcations are implemented and compared exemplarily. It is shown that the Neimark–Sacker system remarkably outperforms the Andronov–Hopf amplifier regarding the CPU usage. Nevertheless, both show a similar input-output behavior over a wide parameter range. Combined with an USB-based control interface connected to a PC, the digital framework provides a powerful instrument to analyze bifurcation based amplifiers.

It is known for decades, that the mammalian hearing process involves an
active amplification within the cochlea

To overcome these drawbacks

Since the Andronov–Hopf and Neimark–Sacker bifurcations both have been
widely described in literature (e.g.

Identical input-output amplitude relations of the Andronov–Hopf and Neimark–Sacker systems for

Amplitude response of the Andronov–Hopf system (dashed) and the Neimark–Sacker system (solid) for

The amplitude response of the Andronov–Hopf system in
Eq. (

Opposed to the Andronov–Hopf bifurcation, the supercritical Neimark–Sacker
bifurcation is a discrete-time system based on the nonlinear difference
equation

The most important goal for the digital implementation is to build a modular system that has the flexibility to exchange and adjust various parts of the system without the need to rewrite fundamental code. Furthermore, the implementation should provide the possibility to deactivate individual processing steps arbitrarily.

Modular processing chain

The processing steps themselves are based on the digital processing chain
proposed by

The ADSP-21369 is a digital signal processor with Super Harvard Architecture (SHARC), an extension of the Harvard architecture by Analog Devices. The CPU contains a single-instruction multiple-data computational architecture (SIMD) that enables the processor to perform up to 2.4 GFLOPS at 400 MHZ. The special structure of the DSP allows simultaneous writing and reading from a memory block, while processing data on a third block. The read and write operations are performed by serial port hardware blocks with chained DMA support that can communicate with the ADC and DAC via I2S protocol. The three block structure produces a delay of two times the blocklength. To get the total delay of the implementation, the system delay of the filters and amplifiers must be added.

Due to the high dynamic range of the system and the nonlinear compression, a
number format with constant relative error instead of a constant absolute
error seems feasible, so that the 40-bit IEEE floating point arithmetic is
used, which is supported by the DSP. To solve the nonlinear differential
equations of the bifurcation based amplifiers, a 4th-order Runge–Kutta
method is chosen. This method appears to be a good choice related to
stability, convergence and performance

Considering the equations are implemented by highly optimized assembler code,
it is not possible for the user to enter arbitrary differential or difference
equations by the GUI. In the first instance, it can be chosen between the
nonlinear amplifiers based on the Andronov–Hopf and the Neimark–Sacker
bifurcation (see Sect.

Amplitude responses versus frequency for

CPU usages for the Andronov–Hopf and Neimark–Sacker bifurcations.

The implemented framework was measured using an Audio Precision SYS-2522
measurement system. Different characteristic frequencies and bifurcation
parameter values were tested with the Andronov–Hopf and the Neimark–Sacker
systems, shown in Fig.

The performance of the implemented framework is outstanding. It is able to
calculate twenty consecutive sections with about 44 % CPU usage for the
Andronov–Hopf and only 26 % CPU usage for the Neimark–Sacker system.
Table

An implementation of a digital framework is introduced, that has the capability to analyze and compare various bifurcation based amplifiers, exemplarily shown by the Andronov–Hopf and Neimark–Sacker bifurcations. It is shown that the input-output behavior of the Neimark–Sacker system and the Andronov–Hopf system equals over a wide range of parameter sets for higher characteristic frequencies. Furthermore, the Neimark–Sacker system shows a considerable higher performance and robustness. The publication of this article was funded by the open-access fund of Leibniz Universität Hannover. Edited by: J. Anders Reviewed by: two anonymous referees