The next generation DDR5 memory operates at double the frequency of DDR4 memory. At 6.4 Gbit s⁻¹ per port, the transmitted symbols are severely distorted at the receiver. Equalisation can be used to partly recover the distorted signal. In this work, a back-plane channel is analysed to derive the requirements for receiver-side equalisation. Based on these results, different correction methods for DDR5 data buffer front-ends are discussed. The results of the equalisation are shown.

Analog environmental signals must be converted to digital for processing and transmitting. This analog to digital conversion is usually done with a constant rate. To save energy during conversion and transmission this conversion rate can be made adaptable to the signal form, which is called asynchronous A-to-D conversion. Before digital processing the asynchronous sampled data must be interpolated to a constant rate. This interpolation is subject of the article. The work was funded by the DFG.