With increasing radar activities in the automotive, industrial and private sector, there is a need to test radar sensors in their environment. A radar target simulator can help testing radar systems repeatably. In this paper, the authors present a concept of low-cost hardware for radar target simulation. The theoretical foundations are derived and analyzed. An implementation of a demonstrator operating in the 24 GHz ISM band is shown for which the dynamical range simulation was implemented in a FPGA with fast sampling ADCs and DACs. By using a FIR filtering approach a fine discretization of the range could be reached which will furthermore allow an inherent and automatic Doppler simulation by moving the target.

Radar technology was invented in 1904 and is well-known for more than one
century. Nevertheless it has mainly been used for military and air traffic
over seventy years. Radar systems often were bulky (hollow waveguide
plumbing) and expensive. Starting in the seventies, radar has been
investigated for non-military application. In the nineties, radar was firstly
used for automotive applications like adaptive cruise control – e.g. by
Toyota (1997), BMW (1998), Mercedes (1999). Starting from that point, radar
technology became cheaper and easier to fabricate due to the development in
semiconductor technologies and material development (RF substrates,
interconnection technology, etc.) for even higher frequencies. Actually
radars are also applied for industrial purposes (e.g. automation and
measurement applications) and personal safety reasons (e.g. in the car
interior;

In Fig.

Schematic overview about RuT operating with a RaTaSim.

Converting down the transmit signal

Schematic overview of RaTaSim.

It is obvious that when

A radar target simulator must simulate the same wave propagation so that the
output of the radar yields the same signal as described in Eq. (

Let us assume that the RaTaSim consists of an internal RF source which is
very stable at frequency

Both signals are mixed via a double sideband mixer yielding only a real
baseband signal

Diagram about mixing processes and frequencies.

The following equation gives the mathematical description of the up conversion.

For the further development we neglect this frequency component. The
upconverted signal is again transmitted by the TX antenna of the RaTaSim and
received by the RuT, the delay time

The receive signal at the radar-under-test is as follows

Furthermore the first part

The commercial simulators presented in

In this section a radar target simulator with an in-the-band-source is
presented

The formulas as derived in the section before can still be used. But due to
the location of

An in-the-band source has the advantage of dividing the band into two parts
of same bandwidth size. In the baseband channels only signals from

All RF- and baseband electronics are developed in our institution in a
modular approach by using semiconductor components (e.g.

All RF components are designed separately on a four-layer PCB with ROGERS RO4835
top and bottom layer with a FR4 core material and connected by
Rosenberger 02K243 connectors. The complete RaTaSim system is implemented in
a modular way by low-noise amplifiers (LNA), the variable gain amplifier (VGA),
the single sideband mixers including the power divider and the 24 GHz
LO signal source which are connected to each other corresponding to the
schematic given in Fig.

The low-noise amplifier is based on an Analog Devices (formerly Hittite)
HMC751 chip which has a frequency range from 20.0 to 28.0 GHz with a gain of
approx. 25–26 dB. The power supply voltage level is 4 V. The low-noise
amplifier module is shown in Fig.

The variable gain amplifier has a programmable gain between 3 and 16 dB
(maximum power of 24 dBm) between 20 and 28 GHz in steps of 1 dB. The used
Analog Devices HMC997 chip requires a supply voltage of 5 V and is shown in Fig.

Finally the Analog Devices HMC1063LP3E chip is used as passive single
sideband mixer for down- and up-mixing. The

Two orthogonal polarisations of the RuT are processed in parallel. This allows
the considerations of all polarisation types (linearly and circularly
polarized). In contrast to the most RaTaSim systems on the market the
antennas are realized in patch antenna technology with a sufficient high
isolation between RX and TX channel instead of expensive horn antennas. The
complete demonstrator is shown in Fig.

Radar target simulator concept.

Modular 24 GHz LO signal source.

Due to the progress in the semiconductor technology the digitization of the
baseband signal and the digital implementation of the delay with a fast FPGA
offers much flexible processing. The delay is realized by a “virtual”
transmission line based on a FIR approach on a Xilinx Kintex-7 KC705 FPGA
which allows low-latency processing of the digital data. The analog-digital
conversion and the digital-analog conversion must be of high sampling rates,
of high resolution and of low-latency, too, which is realized by a 4DSP FPGA
Mezzanine Cards FMC151. The additional inaccurate Doppler shift which is
caused by the delay in the baseband can be corrected in the FPGA due to the
representation of the wave as complex value. The step-size of the radar
targets will be in the sub-mm range which allows inherently the modeling of
the Doppler effect which has been shown in

Modular 24 GHz low-noise amplifier.

Modular 24 GHz variable gain amplifier.

Modular 24 GHz single sideband mixer with commercial power amplifier.

A simple shift register with programmable taps can be used for this purpose.
According the Shannon sampling theorem a minimum sampling rate of 250 MSPS is
needed for operation which is the clock frequency of the shift register
simultaneously. With 250 MSPS the digital delay line has a minimal resolution
of

generally the impulse response of a rectangular window (which is the sinc-function) is infinitely long, but only a filter with finite number of coefficients can be realized for FIR filtering;

the filter is non-causal.

Traveling wave antenna patch array with six elements.

Modular 24 GHz RF circuitry with digital electronics (FPGA and ADC/DAC-board) on a wooden frame.

Coefficients example with 0 and 0.4 samples delay.

The inverse FFT of the limited bandwidth of 250 MHz will result in a
discretization with a time step of 4 ns which corresponds to the 60 cm
propagation path in radar applications. The number of filter coefficients is
dependent from the number of elements of the exponential function. The number
of elements should cover the Shannon theorem, thus the phase shift between
adjacent points in the frequency domain is not greater than 180

Oscilloscope screenshot of baseband signal for CW measurement.

For large distances the number of points could become quite high. For this
reason, and the limited number of existing hardware multipliers in the FPGA,
the delay line has been split. A large FIFO shift register generates the
coarse delay of 0–300 m with 60 cm step resolution and this is appended to
the interpolation filter which has the only task to produce a fine delay
between 2 sampling points. The acausality can simply be bypassed by
pre-sampling, which of course has the disadvantage that the minimally
simulated distance of the radar target simulator is increased. So there has
to be a trade-off between the number of coefficients and the directly related
signal quality as well as the increasing latency and the resource
consumption. A filter length of

The filter coefficients are calculated with Matlab, the so-called coefficient
files were integrated directly with the development environment and stored in
the Block-RAM of the FPGA. Due to the fixed structure of the hardware RAM
blocks, 2048 different variants can be interpolated, which theoretically
corresponds to a distance resolution of 300

The complete demonstrator is tested with a 24 GHz laboratory radar (RuT)
based on the ADF5901 and ADF5904 ICs from Analog Devices. The baseband output
of the the RuT has been connected to a Keysight MSOX2014A Mixed Signal
Oscilloscope with a Fourier transform option. The first measurement was a
classical CW-measurement with a frequency of 24.00 GHz and the simulated
target is moving with 11.875 m s

The baseband output is measured and the Doppler frequency is determined by
Fourier transform with 950 Hz which is equivalent to the analytical result of
the following equation

The rough baseband signal (yellow) is Fourier transformed for which two peaks
are observable. The frequency of the first peak is 7900 Hz while the
frequency of the second peak is 9800 Hz. The mean value of both frequencies
is

Oscilloscope screenshot of baseband signal for FMCW measurement.

With the formula

In this paper a low-cost implementation of a radar target simulator has been
presented. Starting with an introduction into radar target simulation, an
overview was given shortly. Afterwards the theoretical foundations of radar
target simulations were given in a mathematical way with the focus on both
double and single sideband mixers. The generated frequencies and their
location inside and outside of the band of interest were investigated. Out of
that investigation, a concept for a complex-valued transmission line modeling
with an

Due to transformation of a shifted filter function from the frequency domain to the time domain, the finite number of filter coefficients for the FIR filter have been determined. In order to keep resources, the digital delay line was split into two segments. The first delay segment allows for rough delay steps with a size of 60 cm. The second delay module enables a very fine discretization of the range. This manner permits a very low-cost implementation of the radar target simulator in the 24 GHz ISM band. A correct Doppler and range evaluation showed that the concept is valid and could be used for series-development of the hardware. In a next step, a new design of the RF and baseband electronics will be developed which will bring any modular components together, allowing an integration into a housing.

No data sets were used in this article. The FPGA code is not public and are only available from the corresponding author upon request.

ARD conceived of the present idea and the theory. ARD supervise the project. MS put the complete electronics into operation and implemented the hardware description in VHDL. SM designed the RF-modules and put these into operation.

The authors declare that they have no conflict of interest.

This article is part of the special issue “Kleinheubacher Berichte 2017”. It is a result of the Kleinheubacher Tagung 2017, Miltenberg, Germany, 25–27 September 2017.

The author would like to thank ANALOG DEVICES, especially Rudolf Wihl, Dirk Legens, Bernd Krätzig and Christian Eisenschmidt for the kind support. Edited by: Madhu Chandra Reviewed by: Andreas Danklmayer and one anonymous referee