This paper presents a receiver signal strength detector based on a discrete
Fourier transform implementation. The energy detection algorithm has been
designed and measured using a custom multi-standard transceiver ASIC with a
low-IF receiver at 0.5, 1 and 2

Short range wireless systems with low power consumption are increasingly used
for communication of sensor networks. The communication of these networks
usually takes place on three bands, which are also used for a various range
of common standards. WiFi, Bluetooth or Bluetooth LE are located in the
2.4

With the increased unlicensed use of these bands by various standards, listen
before talk functionality is getting more important to ensure a reliable
communication. These

The low-IF receiver (RX) architecture with

Common single band transceiver architectures like the one presented by

This work presents a digital implementation for RSSI calculation based on a
discrete Fourier transform algorithm without area consuming digital
multipliers. Furthermore, the RSSI quality is monitored during RSSI
calculation to minimize the computation time. The algorithm directly
processes the oversampled

The presented RSSI calculation has been designed and tested using synthesized VHDL code executed on an FPGA and connected to a custom triple-band multi-standard transceiver ASIC. An overview of the used RX front-end, the requirements for energy detection and the implementation will be given in the following sections. Subsequently, the RSSI calculation algorithm will be discussed in detail and solutions for an area efficient implementation are given. Furthermore, the measurement setup is presented and the results are shown and compared to analog implementations of ED.

Block diagram of the RX front-end.

An overview of the relevant parts of the transceiver ASIC is shown as a block
diagram of the RX architecture in Fig.

The Fourier transform is a well known and widely used method to analyze a
signal in frequency domain. In Fig.

FFT of single bit

The FFT proves to be an efficient algorithm to calculate the entire frequency
spectrum

Block diagram of the expanded Goertzel filter.

One approach to the DFT implementation is the Goertzel algorithm. The
Goertzel algorithm transfer function is shown in Eq. (

The resulting algorithm works well with CPUs or DSPs, which have a build-in
multiplying unit with sufficient word length, because it reduces the clock
cycles required for a complex multiplication to those of a single real
multiplication. A VLSI implementation does not benefit in the same way from
the reduced multiplication effort, since the complex multiplier has to be
implemented in hardware. Furthermore, the real multiplication requires
considerable word length, since every error induced by quantization is
multiplied in the following cycles. The word length in this case is dominated
by the word length of the constant

The DFT can also be directly implemented to compute only a single frequency
bin instead of multiple bins as it would be necessary for a spectral range.
In Eq. (

However, the DFT works well with

Block diagram of the discrete Fourier transform.

Block diagram of the RSSI hardware implementation.

The presented architecture, depicted in Fig.

The calculation of the DFT is shown as the core processing part in the left
section in Fig.

Regarding the LUT values the exponential term in Eq. (

The input is a complex value defined by the

LUT signal selection for single bit complex multiplication.

For the detection of the DC value the coefficient

The L1-norm is a sufficient method to be used in an RSSI detection. Shown in
Eq. (

For logarithm calculation the value is, as discussed by

Block diagram of logarithm calculation.

The difference of the last two RSSI values is evaluated using an approximate derivative of the RSSI signal. Once the RSSI has converged, the absolute value of this difference drops below a threshold and the RSSI calculation can be stopped. Furthermore, the current slope is given out alongside the RSSI, giving a factor for RSSI quality estimation.

Comparison of the proposed digital algorithm with analog limiting amplifier based implementations.

Development of the RSSI during simulation over run time for an input power of

Figure

Measurement of RSSI, standard deviation, and error over input power.

The design functionality has also been verified in measurements using VHDL
code synthesized on a Xilinx Virtex 5 board. The design was tested using the
existing transceiver ASIC in receive operation as presented in
Sect.

Additionally, the error of the measured RSSI towards an ideal regression is
shown in

In order to integrate the ED within the transceiver ASIC a synthesis for a

A receiver signal strength detection algorithm based on a discrete Fourier
transform algorithm has been presented. It evaluates the single bit output
data stream of a

The raw data for simulation, simulation output data and
measurement results are available at Zenodo (

The authors declare that they have no conflict of interest.

This article is part of the special issue “Kleinheubacher Berichte 2017”. It is a result of the Kleinheubacher Tagung 2017, Miltenberg, Germany, 25–27 September 2017.

The authors acknowledge the financial support by the German Federal Ministry of Education and Research (FKZ 16 ESEO154) and the Electronic Components and Systems for European Leadership Joint Undertaking under grant agreement No. 737434.Edited by: Jens Anders Reviewed by: two anonymous referees