Digital Component Separator for future W-CDMA-LINC Transmitters implemented on an FPGA

Gerhard, W.; Knöchel, R.

doi:https://doi.org/10.5194/ars-3-239-2005

Articles | Volume 3

https://doi.org/10.5194/ars-3-239-2005

© Author(s) 2005. This work is licensed under
the Creative Commons Attribution-NonCommercial-ShareAlike 2.5 License.

https://doi.org/10.5194/ars-3-239-2005

© Author(s) 2005. This work is licensed under
the Creative Commons Attribution-NonCommercial-ShareAlike 2.5 License.

Articles | Volume 3

12 May 2005

| 12 May 2005

Digital Component Separator for future W-CDMA-LINC Transmitters implemented on an FPGA

W. Gerhard and R. Knöchel

Abstract. This paper presents the implementation of a Digital-Component-Separator (DCS) for a LINC-transmitter (linear amplification using nonlinear components) on an FPGA (field programmable gate array). It investigates and estimates the bandwidth requirements for such a LINC system. The influence of bandwidth limitations on a digitally based LINC-transmitter for W-CDMA utilization is studied by simulations. Furthermore a LINC transmitter is proposed which employs a flexible image-reject- or a direct up-conversion-architecture for transmission of single or combined multi-carrier/channel W-CDMA signals using the phase-modulation approach. The sampling frequency can be chosen at a value up to 32 times (122.88MHz) the symbol rate of the W-CDMA chip rate of 3.84Mbits/s. Measurement results for a LINC transmitter are presented and discussed.