Timing violations due to VDD/VSS bounce

Eireiner, M.; Henzler, S.; Berthold, J.; Pacha, C.; Georgakos, G.; Schmitt-Landsiedel, D.

doi:https://doi.org/10.5194/ars-4-197-2006

Articles | Volume 4

https://doi.org/10.5194/ars-4-197-2006

© Author(s) 2006. This work is licensed under
the Creative Commons Attribution-NonCommercial-ShareAlike 2.5 License.

https://doi.org/10.5194/ars-4-197-2006

© Author(s) 2006. This work is licensed under
the Creative Commons Attribution-NonCommercial-ShareAlike 2.5 License.

Articles | Volume 4

06 Sep 2006

| 06 Sep 2006

Timing violations due to V_DD/V_SS bounce

M. Eireiner, S. Henzler, J. Berthold, C. Pacha, G. Georgakos, and D. Schmitt-Landsiedel

Abstract. The effect of power supply noise in on-chip power grids and its implications on the path delay in digital circuits is examined. The simulation results show that IR-Drop and the resulting path delay are strongly affected by the layout of the circuit. Power grid design measures to reduce IR-Drop, as well as their area and performance implications are discussed.