Articles | Volume 4
https://doi.org/10.5194/ars-4-197-2006
https://doi.org/10.5194/ars-4-197-2006
06 Sep 2006
06 Sep 2006

Timing violations due to VDD/VSS bounce

M. Eireiner, S. Henzler, J. Berthold, C. Pacha, G. Georgakos, and D. Schmitt-Landsiedel

Abstract. The effect of power supply noise in on-chip power grids and its implications on the path delay in digital circuits is examined. The simulation results show that IR-Drop and the resulting path delay are strongly affected by the layout of the circuit. Power grid design measures to reduce IR-Drop, as well as their area and performance implications are discussed.

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