<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE article PUBLIC "-//NLM//DTD Journal Publishing DTD v3.0 20080202//EN" "https://jats.nlm.nih.gov/nlm-dtd/publishing/3.0/journalpublishing3.dtd">
<article xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" article-type="research-article" dtd-version="3.0" xml:lang="en">
<front>
<journal-meta>
<journal-id journal-id-type="publisher">ARS</journal-id>
<journal-title-group>
<journal-title>Advances in Radio Science</journal-title>
<abbrev-journal-title abbrev-type="publisher">ARS</abbrev-journal-title>
<abbrev-journal-title abbrev-type="nlm-ta">Adv. Radio Sci.</abbrev-journal-title>
</journal-title-group>
<issn pub-type="epub">1684-9973</issn>
<publisher><publisher-name>Copernicus Publications</publisher-name>
<publisher-loc>Göttingen, Germany</publisher-loc>
</publisher>
</journal-meta>
<article-meta>
<article-id pub-id-type="doi">10.5194/ars-4-269-2006</article-id>
<title-group>
<article-title>Monotonic transition based forward body bias for dual threshold voltage low power embedded processors</article-title>
</title-group>
<contrib-group><contrib contrib-type="author" xlink:type="simple"><name name-style="western"><surname>Jayapal</surname>
<given-names>S.</given-names>
</name>
<xref ref-type="aff" rid="aff1">
<sup>1</sup>
</xref>
</contrib>
<contrib contrib-type="author" xlink:type="simple"><name name-style="western"><surname>Manoli</surname>
<given-names>Y.</given-names>
</name>
<xref ref-type="aff" rid="aff1">
<sup>1</sup>
</xref>
</contrib>
</contrib-group><aff id="aff1">
<label>1</label>
<addr-line>Chair of  Microelectronics, Department of Microsystems Engineering (IMTEK), University of Freiburg, Georges-Koehler-Allee 102, 79110 Freiburg, Germany</addr-line>
</aff>
<pub-date pub-type="epub">
<day>06</day>
<month>09</month>
<year>2006</year>
</pub-date>
<volume>4</volume>
<fpage>269</fpage>
<lpage>273</lpage>
<permissions>
<copyright-statement>Copyright: &#x000a9; 2006 S. Jayapal</copyright-statement>
<copyright-year>2006</copyright-year>
<license license-type="open-access">
<license-p>This work is licensed under the Creative Commons Attribution-NonCommercial-ShareAlike 2.5 Generic License. To view a copy of this licence, visit <ext-link ext-link-type="uri"  xlink:href="https://creativecommons.org/licenses/by-nc-sa/2.5/">https://creativecommons.org/licenses/by-nc-sa/2.5/</ext-link></license-p>
</license>
</permissions>
<self-uri xlink:href="https://ars.copernicus.org/articles/4/269/2006/ars-4-269-2006.html">This article is available from https://ars.copernicus.org/articles/4/269/2006/ars-4-269-2006.html</self-uri>
<self-uri xlink:href="https://ars.copernicus.org/articles/4/269/2006/ars-4-269-2006.pdf">The full text article is available as a PDF file from https://ars.copernicus.org/articles/4/269/2006/ars-4-269-2006.pdf</self-uri>
<abstract>
<p>Dual threshold voltage and forward body bias techniques are
effective ways to optimally balance the standby leakage power and
performance. In this paper, we propose a novel fine-grained forward
body biasing scheme for monotonic static logic circuits. In the
proposed scheme, the forward body bias is applied to high threshold
voltage of either the pull-up or the pull-down network based on the
evaluation transition and the state of operation. This technique
improves the low skew NAND and NOR circuit performance by 7% and
11%,  high skew NAND and NOR by 8% and 13% respectively. It
reduces both active and standby leakage power as compared to
monotonic static CMOS with dual-&lt;i&gt;V&lt;sub&gt;T&lt;/sub&gt;&lt;/i&gt; technique. The simulations are
carried out using 130 nm mixed mode process technology to validate
our proposed technique.</p>
</abstract>
<counts><page-count count="5"/></counts>
</article-meta>
</front>
<body/>
<back>
<ref-list>
<title>References</title>
<ref id="ref1">
<label>1</label><mixed-citation publication-type="other" xlink:type="simple"> v Arnim,~K., Borinski,~E., Seegebrecht,~P., Fiedler,~H., Brederlow,~R., Thewes,~R., Berthold,~J., and Pacha,~C.: Efficiency of Body Biasing in 90 nm CMOS for Low Power Digital Circuits, ESSCIRC, 175&amp;ndash;178, 2004.  </mixed-citation>
</ref>
<ref id="ref2">
<label>2</label><mixed-citation publication-type="other" xlink:type="simple"> Jayapal,~S., Huang,~R., Ramachandran,~S., Bhutada,~R., \vadjustand Manoli,~Y.: Optimization of Electr. Power Consumption in Wireless Sensor Nodes, 8th Euromicro conf. on Digital Syst. Design (DSD), 165&amp;ndash;169, 2005a. </mixed-citation>
</ref>
<ref id="ref3">
<label>3</label><mixed-citation publication-type="other" xlink:type="simple"> Jayapal,~S., Sudalaiyandi,~S., and Manoli,~Y.: Efficiency of Leakage Reduction on Different Static Logic Styles for Embedded Applications with High Standby to Active Ratio, Int. Symp. on System-on-Chip (SoC), 151&amp;ndash;154, 2005b. </mixed-citation>
</ref>
<ref id="ref4">
<label>4</label><mixed-citation publication-type="other" xlink:type="simple"> Narendra,~S., Keshavarzi,~A., Bloechel,~B., Borkar,~S., and De,~V.: Forward body bias for microprocessors in 130 nm technology generation and beyond, IEEE J. Solid-State Circuits, 38, 696&amp;ndash;701, 2003. </mixed-citation>
</ref>
<ref id="ref5">
<label>5</label><mixed-citation publication-type="other" xlink:type="simple"> Solomatnikov,~A., Somasekhar,~D., Roy,~K., and Koh,~C.-K.: Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family, Int. Conf. Comp. Design, 241&amp;ndash;246, 2000. </mixed-citation>
</ref>
<ref id="ref6">
<label>6</label><mixed-citation publication-type="other" xlink:type="simple"> Thorp,~T., Yee,~G., and Sechen,~C.: Monotonic static CMOS and dual Vt technology, IEEE/ACM Int. Symp. on Low Power Electronics and Design, 151&amp;ndash;155, 1999. </mixed-citation>
</ref>
</ref-list>
</back>
</article>