Articles | Volume 6
Adv. Radio Sci., 6, 245–251, 2008
https://doi.org/10.5194/ars-6-245-2008
Adv. Radio Sci., 6, 245–251, 2008
https://doi.org/10.5194/ars-6-245-2008

  26 May 2008

26 May 2008

ESD full chip simulation: HBM and CDM requirements and simulation approach

E. Franell1, S. Drueen2, H. Gossner2, and D. Schmitt-Landsiedel1 E. Franell et al.
  • 1Institute for Technical Electronics, Technical University Munich, Germany
  • 2Infineon Technologies AG, Munich, Germany

Abstract. Verification of ESD safety on full chip level is a major challenge for IC design. Especially phenomena with their origin in the overall product setup are posing a hurdle on the way to ESD safe products. For stress according to the Charged Device Model (CDM), a stumbling stone for a simulation based analysis is the complex current distribution among a huge number of internal nodes leading to hardly predictable voltage drops inside the circuits.

This paper describes an methodology for Human Body Model (HBM) simulations with an improved ESD-failure coverage and a novel methodology to replace capacitive nodes within a resistive network by current sources for CDM simulation. This enables a highly efficient DC simulation clearly marking CDM relevant design weaknesses allowing for application of this software both during product development and for product verification.

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