A novel technique for CAD-optimization of analog circuits with bipolar transistors

In this paper, a novel approach for robust automatic optimization of analog circuits with bipolar transistors is presented. It includes additional formal parameters into the device model cards, which sweep the model parameters smoothly between the different device types. In this way, not only the sizing, but also the choice of the device type is committed to the optimization tool, thus improving the efficiency of the design process significantly.


Introduction
Very important step in the design of analog integrated circuits is the choice of the device types.The latter is a typical problem especially by the design of BiCMOS circuits.There, the bipolar transistors should be selected among several device types offered by the fabrication foundry, which have only few (or even no) adjustable parameters (X-FAB AG, 2008).In this way, the circuit performance depends strongly on the initial choice of the device types, which is done by the designer and is based mainly on his experience and basic engineering considerations.Once this choice has been made, a subsequent CAD-based circuit optimization is strongly restricted by the insufficient number of remaining adjustable device parameters.
Up to now, few approaches for optimization of the device types exist and are mostly based on discrete optimization methods (e.g.Cadence Design Systems, 2008).Here, we present a novel approach for automatic selection of device types using a gradient-based optimizer.Its general idea is described in Sect. 2 of this paper, with some important remarks about its applicability pointed out in Sect.3. In Sect.4, the optimization process of an integrated BiCMOS buffer am-Correspondence to: B. Dimov (boyko.dimov@imms.de)plifier with moderate complexity is described, thus demonstrating the efficiency of the proposed approach.Section 5 concludes the paper.

General description of the new approach
A typical analog circuit optimization tool can be represented with the 3-level structure shown in Fig. 1.The optimization goal is to find the global minimum of the objective function OBJ(Q), with Q=(q 1 , . . ., q n ) -the vector of the circuit performances under optimization.At each iteration step, a set of design parameters P =(p 1 , . . ., p m ) is generated by the optimizer.The corresponding equivalent electrical circuit is composed and simulated with a SPICE-like electrical simulator, and the resulting performance vector Q is obtained.For this, electrical device models are used with model parameters R=(r 1 , . . ., r k ) specified by the fabrication foundry, i.e.Q=Q(P ,R).
The efficiency of the design process can be improved significantly, if not only the sizing, but also the choice of the type of the devices is performed automatically by the optimization tool.For this, additional design parameters S=(s 1 , . . ., s l ) should be incorporated, which switch between the different device model cards.The latter is schematically shown in Fig. 2. A drawback of this approach is the abrupt change of the corresponding circuit performances Q, which results from the discrete change of the device type.The latter is hardly compatible with any gradient-based optimization techniques, thus prohibiting the utilization of their great fastness.
In order to facilitate the application of gradient-based algorithms, a smooth transition of the circuit performances Q across the whole range of available device types should be ensured.We do this by incorporating the additional design parameters S directly into the device model cards.They are used to map the model cards of the available device Published by Copernicus Publications on behalf of the URSI Landesausschuss in der Bundesrepublik Deutschland e.V.   types into a single model card with redefined model parameters R:R(S)=(r 1 (S), . . ., r k (S)).This is schematically shown in Fig. 3, where the model cards of two PNP bipolar transistor types pnp1 and pnp2 are mapped into the single model card pnp12.In this example, the devices are modeled within the SPICE Gummel-Poon (SGP) model (Gummel and Poon, 1970;Berkner, 2002).Only k=3 model card parameters are considered: R:={BF, VAF, IS}, with BF, VAF, and IS being the forward current gain, the forward Early voltage, and the saturation current model parameters.One additional parameters s is used to map the pnp1 and pnp2 model cards: S:={s}.As also shown in Fig. 3, this mapping is assumed to be: pnp12| s=0 ↔pnp1; pnp12| s=1 ↔pnp2, i.e. r 1 (0)=bf1, r 2 (0)=vaf1, r 3 (0)=is1, r 1 (1)=bf2, r 2 (1)=vaf2, r 3 (1)=is2.If the functions r 1 (S), . . ., r k (S) are continuous, they sweep the circuit performances also continuously through the model cards of all available device types: (1) In this way, the automatic choice of the device type can be supported also by deterministic optimization algorithms, thus increasing significantly the efficiency of the optimization process.However, the following requirements should also be fulfilled: -the sequence, in which the device types are swept, should be chosen with respect to minimize the number of the local extrema of the circuit performances, i.e. S should sweep the circuit performances q 1 , . . ., q n as monotonic as possible.
-because the sweeping functions r 1 (S), . . ., r k (S) are continuous, nonphysical interim values of the model parameters R(S) (and thus also of the circuit performances Q(P ,R(S))) cannot be avoided, however their evaluation as optimum ones should be suppressed somehow.
-the number l of the model sweeping parameters s 1 , . . ., s l should be kept as low as possible, because it directly increases the total order of the optimization problem.
Below, a possible strategy to fulfill these requirements is described.
3 Implementation of the new approach

Optimal arrangement of the device types
Although there is no full equivalence between the total circuit performance and the performances of the circuit's devices alone, they are usually strongly correlated.Utilizing this correlation, the devices are sorted with respect to their figures-of-merit, which have to be swept with S as monotonic as possible.Ideally, this sorting requirement should be fulfilled about all device's figures-of-merit, but this is possible only in case of device models with few model parameters and figures-of-merit (e.g.resistors and capacitors).The optimal choice of the type of such devices is usually a trivial task; the real challenge is met with the complex device models (e.g.transistors) having many and often weak correlated figures-of-merit.In this case, a simultaneous monotonic sweeping of all figures-of-merit is not possible, but the designer should ensure it for those figures-of-merit dominating the device performance within the particular application.As a typical example for this, the sorting of amplifier's transistors can be considered.The matching of the transistors in case of differential amplification is essential for the circuit functionality.Therefore, the designer should include it within the dominating sorting criteria, contrary to the case of nondifferential amplification.This arrangement can be performed dynamically also about devices with equal models within one and the same analog circuit.Considering again amplifier's transistors, the dominant figures-of-merit for input-stage ones are usually the generated noise and the transit frequency.However, they are less important about output-stage transistors, whose highcurrent performance is more dominant.Therefore, the device types of the input and output transistors can be sorted (and correspondingly swept with S) in different ways, although the devices have identical models and thus share one and the same set of possible device types.
It should be pointed out, that the device type arrangement described above is performed before the circuit's optimization, i.e. at an early design stage, when even the dc operating point may be unknown.Therefore, the devices' figures-ofmerit should be calculated out of the context of the particular analog circuit.Being dynamically dependent on both the circuit functionality in general and the device's specific function within the circuit, the device types arrangement should be usually performed multiple times during the circuit's design phase.Therefore, an efficient approach for automatic evaluation of the devices' figures-of-merit should be implemented in the optimization strategy.
One very promising candidate for this is the direct analytic approach described in Dimov et al. (2008).It is based on explicit analytic formulas calculating the device's figuresof-merit directly from its model card.Such estimation requires no electrical simulations or similar numerical calculation techniques, thus being extremely robust and fast.The formulas proposed in Dimov et al. (2008) can be easily implemented in self-written hand calculators or conventional computation tools such as Wolfram Research (2008).In this way, the device's figures-of-merit are evaluated immediately, and the device type arrangement is performed with negligible computation efforts.

Choice of the sweeping functions R(S)
As pointed out in Sect. 2 of the paper, the main advantage of the proposed novel approach is its compatibility with gradient-based optimization algorithms.The gradient calculations are done numerically using finite differences (Graeb, 2007).About the optimization problem considered in this paper, the latter can be expressed using Eq.(1): , with superscript n representing the n th optimization iteration.Despite of the particular optimization strategies implemented into the gradient-based algorithm, the decision about the next design parameter set (P n+1 , S n+1 ) as well as the next numeric step ( P n+1 , S n+1 ) is derived always from the gradient(s) of the objective function calculated at the current (and optionally: previous) design parameter set(s) (Graeb, 2007).Therefore, the sweeping functions R(S) should be not only continuous and thus numerically differentiable, but their gradients calculated at nonphysical interim values of the device model parameters should always push the optimization algorithm towards feasible model parameter values.
This requirement is successfully met, if piece-wise linear sweeping functions are used.About the simple example described with Fig. 3, the sweeping functions have to be defined as:

Minimizing the number l of the sweeping parameters
Being incorporated into the device model cards, the model sweeping parameters s 1 , . . ., s l appear as additional instance parameters of the devices under optimization.Let assume, that i≤l sweeping parameters are used to sweep the model card parameters of j uncorrelated devices from one and the same type.The latter results in i×j additional uncorrelated optimization parameters, i.e. the total order of the optimization problem increases rapidly with i.Therefore, the number of the sweeping parameters should be kept as low as possible.
A powerful way for this is the multiple reusing of already existing instance parameters.This idea will be illustrated about two types of bipolar transistors -QNA and QNB, which have to be merged in a common model card QNAB without increasing the number of optimized parameters.Let QNA be a scalable transistor with instance parameter EA=1. . . 10 corresponding to emitter areas 1. . . 10 µm2 , respectively.Then, its model card parameters are functions of EA, which will be designated as R QNA (EA).Let QNB be a transistor with fixed layout and emitter area of 1 µm 2 , i.e. having no instance parameters.Its model card parameters will be designated as R QNB .A possible definition of the model card parameters R QNAB (s) is:    i.e. the single sweeping parameter s incorporated into the model card of QNAB is used both to sweep linearly between QNB and QNA and to model the emitter area of QNA, thus replacing the instance parameter EA.
Note, that the proposed arrangement and the resulting sweeping functions R QNAB (s) should fulfill all sorting preconditions described in Sects.3.1 and 3.2.Otherwise, local minima of the objective function OBJ(Q) can appear for interim values of s between 0.5 and 1 pointing to nonexistent type of the QNAB device.
Another typical problem is the arrangement of devices with identical instance parameters, but different feasible ranges of the latter.
Considering again two bipolar transistor types QNC and QND, let both have variable emitter area EA, i.e. model card parameters being functions of EA: R QNC (EA) and R QND (EA), respectively.
Let EA QNC,min ≤EA≤EA QNC,max and EA QND,min ≤EA≤EA QND,max are the feasible ranges of the emitter area of QNC and QND, respectively.
Without loss of generality, let us assume: EA QNC,min ≤EA QND,min <EA QNC,max ≤EA QND,max .The aim is again to merge the both device types in a common model card QNCD with minimum number of additional sweeping parameters.For this, the sweeping parameter s 1 is introduced and the model cards of QNC and QND are extended as: The latter is schematically shown in Fig. 4. It should be pointed out, that again one of the sweeping parameters (i.e.s 1 ) is used also to replace the instance parameter EA, thus reducing the order of the optimization problem.Note, that with such device type arrangement, nonphysical parameter values (e.g.s 2 =0, EA QNC,max <s 1 ≤EA QND,max ) may be evaluated as final optimum, but they can be rounded to the closest feasible parameter set (e.g.s 2 =0, s 1 =EA QNC,max ) without loosing the optimum circuit performance Q.

Application of the new approach
The described novel approach for automatic optimization of the device types has been tested optimizing the BiCMOS integrated buffer amplifier with moderate complexity proposed in Furth and Andreou (1993).Its electrical scheme is shown in Fig. 5.The circuit contains seven bipolar transistors and has to be realized with a 0.6 µm BiCMOS fabrication technology providing 13 different types of bipolar transistors with fixed as well as continuously and discrete scalable emitter lengths.
The goal of the optimization has been the increasing of the bandwidth of the amplifier, keeping the rest of its performances within the specification constraints (see Table 1).Therefore, the transit frequency has been chosen to be the dominant figure-of-merit for the arrangement of the whole variety of bipolar transistors.The arrangement has been done with two sweeping parameters, one of which has replaced the emitter length instance parameters, as described in Sect.3.3.The smooth sweeping between the different transistor types has been done using piece-wise linear functions.The amplifier has been optimized with the commercial analog circuit optimization tool WiCkeD (MunEDA GmbH, 2008).By this, only gradient-based optimization strategies have been used.During this test, only the bipolar transistors' parameters (type and sizing) have been optimized; all other circuit devices have been kept unchanged.
The results are given in Table 1: the bandwidth has been improved significantly at the cost of reasonable phase margin degradation, keeping all other performances nearly unchanged.This optimum has been achieved with only 5 optimization steps, thus demonstrating not only the efficiency of the proposed novel approach, but also its excellent compatibility with the modern CAD-tools for analog circuit design.

Conclusions
A novel approach for analog circuit optimization involving automatic selection of the device types has been presented.Including additional formal parameters to the model cards of the devices, it permits a smooth transition of the model parameters across the range of available device types.In this way, the optimal device type can be evaluated using gradientbased optimization strategies.At the same time, the proposed approach is fully compatible with stochastic optimization algorithms.Thus, the universality of the latter can be utilized together with the efficiency of the deterministic optimization techniques.

Fig. 2 .
Fig. 2. Modified structure of analog circuit optimization tool permitting automatic selection of the device types.

Figure 3 .
Figure 3. Bipolar transistor types pnp1 and pnp2 merged into the single model card pnp12.

Figure 4 .
Figure 4. Arrangement in case of different feasible ranges of the instance parameters.

Fig. 4 .Figure 5 .
Fig. 4. Arrangement in case of different feasible ranges of the instance parameters.

Table 1 .
Performances of the buffer amplifier: specification, before, and after the optimization.