High-voltage ( 100 V ) Chipfilm TM single-crystal silicon LDMOS transistor for integrated driver circuits in flexible displays

System-in-Foil (SiF) is an emerging field of largearea polymer electronics that employs new materials such as conductive polymers and electrophoretic micro-capsules (EInk) along with ultra-thin and thus flexible chips. In flexible displays, the integration of gate and source drivers onto the flexible part increases the yield and enhances the reliability of the system. In this work we propose a high-voltage ChipfilmTM lateral diffused MOS transistor (LDMOS) structure on ultra-thin single-crystalline silicon chips. The fabrication process is compatible with CMOS standard processing. This LDMOS structure proves to be well suited for providing adequately large switching voltages in spite of the thin ( <10μm) substrate. A breakdown voltage of more than 100 volts with drain-to-source saturation current I ds(sat)≈85μA/μm for NLDMOS and Ids(sat)≈20μA/μm for P-LDMOS is predicted through process and device simulations.


Introduction
Presently, the primary focus of electronic display industry is the large-area polymer electronics.This field employs new materials and techniques to build thin, bendable and highresolution displays (Allen, 2005).The implementation of ultra-thin and thus flexible driver chips allows for improvements since such chips can be placed onto the flexible parts of the display, thus shortening the wiring length, and paving the way to larger flexible displays in the future.
A typical flexible display consists of a flexible substrate, an active matrix backplane, a layer with electrophoretic micro-capsules, and a transparent electrode.In the active matrix backplane an array of thin-film transistors (TFT) is used Correspondence to: A. Asif (aliasif@ims-chips.de) to provide the required voltage across each electrophoretic micro-capsule, according to an input address signal.In contrast to Si-bulk transistors, these TFT transistors require gate and drain voltages up to few tens of volts (Bai et al., 2007).In order to drive these thin-film transistors, source and gate driver circuits are required.These driver circuits are typically placed on the rigid part of the display near the edge, connecting to the TFT matrix through tape automated bonding (TAB).The drawback of this placement is that it increases the physical size and weight of the product.Moreover, the system also becomes unreliable especially in rugged environment.The integration of source and gate driver circuits onto the flexible part will reduce the length of the interconnects, as mentioned above.
Integration of organic, a-Si or poly-Si based transistors on flexible substrates can be achieved through large-area fabrication processes (Bock, 2005;Troccoli et al., 2006).An integrated source and gate driver chip using a-Si transistors has already been reported in Venugopal and Allee (2007).The low mobility of carriers in organic/a-Si/poly-Si based transistors, however, makes them unsuitable for high performance systems.Crystalline silicon transistors are better suited for efficient systems but the high processing temperatures required for their fabrication prevent from direct fabrication on flexible substrates.A solution comes from transferring pre-fabricated thin-film single-crystal silicon transistors onto flexible substrates (Li et al., 2006).Good resistance to fatigue and mechanical flexibility of pre-fabricated singlecrystalline silicon MOSFETs on organic substrates has been reported in Li et al. (2006).But, most of the research work has focused on low-voltage single-crystal MOSFETs.The design of a thin-film high-voltage MOS (HVMOS) structure in single-crystalline silicon for flexible applications has not seen much attention yet due to unavailability of a suitable thin-chip technology.
The conventional scheme of a HVMOS is the lateral diffused MOS (LDMOS) transistor structure.This structure 5 µm.However, the drift region depth in PMOS is about 0.6 µm whereas in is about 2.0 µm.The well depth is almost 3.0 µm.In this structure an length of 5 µm for both drain field plate and gate field plate is used. of the gate oxide is 25 nm.The field oxide thicknesses under the gate and drain field plate are 0.8 µm and 1.5 µm, respectively.transistors have identical effective channel length ≈ 3.5 µm and drift region 15 µm.However, the drift region depth in PMOS is about 0.6 µm whereas in it is about 2.0 µm.The well depth is almost 3.0 µm.In this structure an d length of 5 µm for both drain field plate and gate field plate is used.ss of the gate oxide is 25 nm.The field oxide thicknesses under the gate te and drain field plate are 0.8 µm and 1.5 µm, respectively.makes use of a drift region and a deep well to withstand high voltages (Sigg et al., 1972).RESURF technique (Ludikhuize, 2000) further enhances the efficiency of the device by increasing the breakdown voltage level.Other approaches could also be used for increasing the breakdown voltage and reduce the on-resistance R on , such as double RESURF technique by using internal field rings, buried layers, triple well architecture and super-junction LDMOS transistors (Hossain et al., 2002;Nezar and Salama, 1991;Liaw et al., 2007;Puchner et al., 2007;Park and Salama, 2006).
In this paper, we propose a single-crystalline silicon based LDMOS transistor structure for flexible displays, built on a thin silicon chip with a breakdown voltage limit of more than 100 volts.The process steps are compatible with a CMOS standard process flow.We use the device in a high-voltage switch circuit for integrated source/data drivers and discuss the issue of efficiency enhancement.

Device structure and fabrication
A SiF requires ultra-thin chips.A chip thinner than 20 µm has excellent flexibility and stability.The minimum bending radius, which is limited by the maximum strain of silicon, reduces toward smaller chip thickness.Thin chips result from post-process back-grinding of conventional CMOS wafers to the desired thickness.At thickness levels of a few tens of microns, post-process grinding is known to produce defects that propagate to the active regions at the chip surface.Also, the mechanical stability of back-grinded thin chips may be degraded by defect.The recently introduced Chipfilm™ technology circumvents these issues by pre-processing a wafer with buried cavities, which a piori define the chip thickness, prior to CMOS integration (Zimmermann et al., 2006).The Chipfilm™ process results in a p + backside layer having 1 µm-1.5 µm thickness, upon which the device structures can be fabricated.This is in contrast to thin-film SOI transistors where the device is fabricated on an insulator.A drawback of this p + layer is the out-diffusion into the epitaxial layer grown above.This out-diffusion takes place during the high temperature process steps e.g.well drive-in and fieldoxide growth.The more the out-diffusion approaches the well-substrate junction the more the breakdown voltage limit is decreased.Therefore, the fabrication steps should be tailored for minimum thermal budget in order to minimize outdiffusion from p + layer.
The high-voltage thin-film LDMOS structure is developed and simulated by using the process simulator Athena from Silvaco.The cross-sectional views of high-voltage NMOS and PMOS transistors are shown in Fig. 1a and 1b.The conceptional structure of the device is identical to the conventional lateral diffused MOS (LDMOS) transistor having a RESURF structure and a drain field-plate.The drain fieldplate helps in increasing the breakdown voltage limit and in reducing R on .Both NMOS and PMOS transistors have identical effective channel length ≈3.5 µm and drift region length ≈15 µm.However, the drift region depth in PMOS is about 0.6 µm whereas in NMOS it is about 2.0 µm.The well depth is almost 3.0 µm.In this structure an optimised length of 5 µm for both drain field plate and gate field plate is used.Thickness of the gate oxide is 25 nm.The field oxide thicknesses under the gate field-plate and drain field plate are 0.8 µm and 1.5 µm, respectively.nm) layer and then filling the trenches by depositing an oxide layer.The purpose litting the epitaxial growth into two parts and applying a trench formation for fielde is to reduce the overall thermal budget.The remaining process steps of gatee growth, poly-gate deposition, source/drain region implant and metallization are similar to the conventional CMOS process flow. is done by etching trenches into silicon, growing a relatively thin field-oxide (~ nm) layer and then filling the trenches by depositing an oxide layer.The purpose litting the epitaxial growth into two parts and applying a trench formation for fielde is to reduce the overall thermal budget.The remaining process steps of gatee growth, poly-gate deposition, source/drain region implant and metallization are similar to the conventional CMOS process flow.The fabrication process starts by growing a 7 µm thick ptype epitaxial layer over the p + layer.The epitaxial layer is grown in two steps, i.e. growth of a 5 µm thick epitaxial layer followed by a well implant and further growth of a 2 µm thick epitaxial layer, again followed by the same well implant.After well implantation, a drive-in step is done at 1150 • C to attain a well depth of approximately 3 µm.Then, the drift-region implantation is performed followed by the field-oxide growth.The field-oxide growth step is done by etching trenches into silicon, growing a relatively thin fieldoxide (∼100 nm) layer and then filling the trenches by depositing an oxide layer.The purpose of splitting the epitaxial growth into two parts and applying a trench formation for field-oxide is to reduce the overall thermal budget.The remaining process steps of gate-oxide growth, poly-gate deposition, source/drain region implant and metallization are very similar to the conventional CMOS process flow.From Fig. 2a and 3a one can notice that P-LDMOS has a higher threshold voltag about 1.2 volts compared to 0.6 volts for the N-LDMOS.This variation comes f the difference in doping density in the P-LDMOS channel (~ 10 16 cm -3 ) compa with that in the N-LDMOS channel (~ 10 15 cm -3 ).In  From Fig. 2a and 3a one can notice that P-LDMOS has a higher threshold voltag about 1.2 volts compared to 0.6 volts for the N-LDMOS.This variation comes f the difference in doping density in the P-LDMOS channel (~ 10 16 cm -3 ) compa with that in the N-LDMOS channel (~ 10 15 cm -3 ).In From Figs. 2a and 3a one can notice that P-LDMOS has a higher threshold voltage of about 1.2 volts compared to 0.6 volts for the N-LDMOS.This variation comes from the difference in doping density in the P-LDMOS channel (∼10 16 cm −3 ) compared with that in the N-LDMOS channel (∼10 15 cm −3 ).In Fig. 2b a quasi-saturation state appears between linear and saturation region.It is represented by a relatively straight line instead of a sharp edge during the transition from linear to saturation state.The quasi-saturation state appears because of velocity saturation.By changing input signal and the gate terminals of HVMOS transistors of the output stage.These level-shifters are designed with minimum static power dissipation, high-speed switching and minimum circuit-area, which directly influence the cost and yield figures of the product.In general one has to make a compromise between minimum circuit area and circuit efficiency.A general circuit topology of a high-voltage CMOS switch is shown in Fig. 4. In this schematic a low-voltage input signal is directly and simultaneously applied to the driver circuits for the HVPMOS and HVNMOS of the output stage.These driver circuits ensure the required voltage levels according to the input signal at the gate terminals of HVPMOS and HVNMOS transistor of the output stage.The switch provides a high-voltage output signal in phase with the low-voltage input signal.Performance comparison -In this section, we compare the performance of the circuit shown in Fig. 5 with that of another one reported in [19].The schematic of the circuit from literature [19] is depicted in Fig. 6.Both use the same circuit topology illustrated in Fig. 4.
For the analysis and comparison of the performance of both circuits, we extract the parameters for high-voltage thin-film LDMOS transistor structures and fit them to a compact transistor model.The transistor model is then used in LTSPICE simulation.The simulation is performed for an input signal frequency of 20 kHz and a load of 100 pF.The length Fig. 6. Circuit diagram of high-voltage switch from literature (Declercq et al., 1993).

High-voltage switch for source/data drivers
A complementary arrangement of MOS transistors is often used in the output stage of switching circuits.In high-voltage switches a level-shifter is required between the low-voltage input signal and the gate terminals of HVMOS transistors of the output stage.These level-shifters are designed with minimum static power dissipation, high-speed switching and minimum circuit-area, which directly influence the cost and yield figures of the product.In general one has to make a compromise between minimum circuit area and circuit efficiency.
A general circuit topology of a high-voltage CMOS switch is shown in Fig. 4. In this schematic a low-voltage input signal is directly and simultaneously applied to the driver circuits for the HVPMOS and HVNMOS of the output stage.These driver circuits ensure the required voltage levels according to the input signal at the gate terminals of HVPMOS and HVNMOS transistor of the output stage.The switch provides a high-voltage output signal in phase with the lowvoltage input signal.
Figure 5 shows the circuit diagram of the high-voltage switch.Here, transistor M7 is used to drop most of the highvoltage across its drain-source terminals.M4 and M5 are long and narrow channel transistors, resulting in a high cannel resistance.This determines the current to primarily flow through M3, M7 and M8.Transistors M4 and M5, together with M6, are used to drive transistor M3.Transistors M3 and M8 will determine the amount of current through the driver circuit and the voltage level at the combined drain terminals of M3, M7 and M6.(b) Output signal of circuit taken from literature (Declercq et al., 1993).

Performance comparison
In this section, we compare the performance of the circuit shown in Fig. 5 with that of another one reported in Declercq et al. (1993).The schematic of the circuit from literature (Declercq et al., 1993) is depicted in Fig. 6.Both use the same circuit topology illustrated in Fig. 4.
For the analysis and comparison of the performance of both circuits, we extract the parameters for high-voltage thinfilm LDMOS transistor structures and fit them to a compact transistor model.Figure 7a and 7b show the simulation results of the output signal of the circuit from Fig. 5 and the output signal of the circuit design from Declercq et al. (1993), respectively.It can be seen that both circuits are able to provide rail-to-rail voltage at the output terminal.
A. Asif et al.: High-voltage LDMOS transistor for integrated driver circuits In the circuit from Fig. 5, a current of 180 µA flows during the first half cycle of the input signal whereas no current flows during the second half cycle (see Fig. 8a).That relates to an average current of 90 µA per cycle through the driver circuit of the HVPMOS.
Figure 8b illustrates the current through the driver circuit of the HVPMOS for the circuit from Declercq et al. (1993).The upper graph shows the current through driver circuit during the positive half cycle of the input signal whereas the lower graph shows the current during the negative half cycle.During both half cycles 180 µA current flows through the driver circuit.Thus, the average current over a complete cycle of input signal is also 180 µA.
Considering the transistor count, both circuits use the same number of transistors in the output stage and in the driver circuits of HVNMOS transistor.The only difference is in the driver circuit of the HVPMOS transistor, where the circuit from Declercq et al. (1993) uses two high-voltage LDMOS transistors.In contrast, the circuit from Fig. 5 has only one high-voltage LDMOS transistor (see Figs. 5 and 6).This shows that the circuit from Fig. 5 requires smaller circuitarea and dissipates less static-power compared to circuit from Declercq et al. (1993), thus making it more efficient.

Conclusions
We have developed a high-voltage Chipfilm™ LDMOS transistor structure on single-crystalline silicon for flexible electronic display.The process involved is compatible with CMOS standard processing.Simulation results showed that with a silicon film thickness of less than 10 µm, by using the Chipfilm™ process, the LDMOS structure has a breakdown voltage of more than 100 volts for both N-LDMOS and P-LDMOS transistor structures.This LDMOS structure proves to be well suited for use in a driver circuit chip on flexible display backplanes.It also provides adequately large switching voltages.The proposed device will significantly improve the performance of circuits on flexible substrates.Moreover, better circuit design of high-voltage switch for source/data drivers will further enhance the efficiency.
The cross-section of a high-voltage N-LDMOS The cross-section of a high-voltage P-LDMOS ross-sectional view of high-voltage ChipfilmTM LDMOS transistors.(a)The cross-section of a high-voltage N-LDMOS.
characteristics of the devices are obtained by using the device lator Atlas from Silvaco.In Fig. 2a and 2b the input and output characteristics of -voltage Chipfilm TM N-LDMOS are shown.Fig. 3a and 3b show the input and ut characteristic of a high-voltage Chipfilm TM P-LDMOS.(a)Input characteristics of high-voltage Chipfilm™ N-LDMOS.
characteristics of high-voltage Chipfilm TM N-LDMOS.current-voltage characteristics of the devices are obtained by using the device lator Atlas from Silvaco.In Fig. 2a and 2b the input and output characteristics of -voltage Chipfilm TM N-LDMOS are shown.Fig. 3a and 3b show the input and ut characteristic of a high-voltage Chipfilm TM P-LDMOS.(b) Output characteristics of high-voltage Chipfilm™ N-LDMOS.

Figure 3
Figure 3 Device characteristics of high-voltage Chipfilm TM N-LDMOS.
Fig. 2b a quasi-saturation s appears between linear and saturation region.It is represented by a relatively stra line instead of a sharp edge during the transition from linear to saturation state.quasi-saturation state appears because of velocity saturation.By changing d region doping density and threshold adjustment implant this effect can be eliminat The electrical characteristics have shown that the proposed high-voltage Chipfil LDMOS can provide sufficiently large switching voltages.Hence it can fairly well w as a high-voltage switch for the integrated source/data drivers of flexible displays.

Figure 3
Figure 3 Device characteristics of high-voltage Chipfilm TM N-LDMOS.

Figure 4
Figure 4 Block diagram of high-voltage switch circuit topology.

Fig. 5
Fig. 5 shows the circuit diagram of the high-voltage switch.Here, transistor M7 is used to drop most of the high-voltage across its drain-source terminals.M4 and M5 are long and narrow channel transistors, resulting in a high cannel resistance.This determines the current to primarily flow through M3, M7 and M8.Transistors M4 and M5, together with M6, are used to drive transistor M3.Transistors M3 and M8 will determine the amount of current through the driver circuit and the voltage level at the combined drain terminals of M3, M7 and M6.

Fig. 5 .
Fig. 5. Circuit diagram of the high-voltage switch.Transistors M1 and M2 constitute the output stage, transistors M3-M8 form the driver circuit for HVPMOS, transistors M9-M10 make driver circuit for HVNMOS.V dd is a voltage source, input signal provides a square wave signal between 0-5 volts.

Figure 5
Figure 5 Circuit diagram of the high-voltage switch.Transistors M1 and M2 constitute the output stage, transistors M3-M8 form the driver circuit for HVPMOS, transistors M9-M10 make driver circuit for HVNMOS.V dd is a voltage source, Input signal provides a square wave signal between 0-5 volts.

Figure 6
Figure 6 Circuit diagram of high-voltage switch from literature [19].
nd width of high-voltage LDMOS transistors for both P-LDMOS and N-LDMOS are et to L ≈ 3.5 µm and W ≈ 50 µm, respectively.
(a) Output signal of the circuit from Fig. 5 (b) Output signal of circuit taken from literature [19] igure 7 Output signal from high-voltage switches.ig.7a and 7b show the simulation results of the output signal of the circuit from Fig. and the output signal of the circuit design from [19], respectively.It can be seen at both circuits are able to provide rail-to-rail voltage at the output terminal.

( a )
Output signal of the circuit from Fig.5.nd width of high-voltage LDMOS transistors for both P-LDMOS and N-LDMOS are et to L ≈ 3.5 µm and W ≈ 50 µm, respectively.
(a) Output signal of the circuit from Fig. 5 (b) Output signal of circuit taken from literature [19] igure 7 Output signal from high-voltage switches.ig.7a and 7b show the simulation results of the output signal of the circuit from Fig. and the output signal of the circuit design from [19], respectively.It can be seen at both circuits are able to provide rail-to-rail voltage at the output terminal.

Figure 8
Figure 8 Current through the driver circuit of HVPMOS transistors.

Fig. 8b illustratesFigure 8
Fig. 8b illustrates the current through the driver circuit of the HVPMOS for the circ from [19].The upper graph shows the current through driver circuit during the posit half cycle of the input signal whereas the lower graph shows the current during negative half cycle.During both half cycles 180 µA current flows through the dri

Fig. 8b illustrates
Fig. 8b illustrates the current through the driver circuit of the HVPMOS for the circ from [19].The upper graph shows the current through driver circuit during the posit half cycle of the input signal whereas the lower graph shows the current during negative half cycle.During both half cycles 180 µA current flows through the dri