Exploration of dual supply voltage logic synthesis in state-of-the-art ASIC design flows

Mahnke, T.; Stechele, W.; Embacher, M.; Hoeld, W.

doi:https://doi.org/10.5194/ars-1-185-2003

Articles | Volume 1

https://doi.org/10.5194/ars-1-185-2003

© Author(s) 2003. This work is licensed under
the Creative Commons Attribution-NonCommercial-ShareAlike 2.5 License.

https://doi.org/10.5194/ars-1-185-2003

© Author(s) 2003. This work is licensed under
the Creative Commons Attribution-NonCommercial-ShareAlike 2.5 License.

Articles | Volume 1

05 May 2003

| 05 May 2003

Exploration of dual supply voltage logic synthesis in state-of-the-art ASIC design flows

T. Mahnke, W. Stechele, M. Embacher, and W. Hoeld

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May 2013	2	10	1	13
Jun 2013	6	0	6
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Oct 2013	1	5	0	6
Nov 2013	12	0	12
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Jul 2014	1	13	0	14
Aug 2014	4	11	0	15
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Latest update: 21 Nov 2024