Articles | Volume 6
Adv. Radio Sci., 6, 227–232, 2008
https://doi.org/10.5194/ars-6-227-2008
Adv. Radio Sci., 6, 227–232, 2008
https://doi.org/10.5194/ars-6-227-2008

  26 May 2008

26 May 2008

Impact of on-chip inductance on power supply integrity

M. Eireiner1, S. Henzler2, X. Zhang1, J. Berthold2, and D. Schmitt-Landsiedel1 M. Eireiner et al.
  • 1Institute for Technical Electronics, Technical University Munich, Germany
  • 2Infineon Technologies AG, Munich, Germany

Abstract. Based on product related scenarios, the impact of on-chip inductance on power supply integrity is analyzed. The impact of varying current profiles is shown to be minimal. In a regular power grid with regular bump connections, the impact of on-chip inductance on the cycle average of the supply voltage can be neglected, even for a worst case estimation of on-chip inductance. Whereas, the maximum transient power supply drop can be significantly underestimated by neglecting on-chip inductance. The impact of on-chip inductance in a System-on-Chip (SoC) environment also can be neglected if the on-chip inductance is conservativly estimated.

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