Impact of on-chip inductance on power supply integrity

Abstract. Based on product related scenarios, the impact of on-chip inductance on power supply integrity is analyzed. The impact of varying current profiles is shown to be minimal. In a regular power grid with regular bump connections, the impact of on-chip inductance on the cycle average of the supply voltage can be neglected, even for a worst case estimation of on-chip inductance. Whereas, the maximum transient power supply drop can be significantly underestimated by neglecting on-chip inductance. The impact of on-chip inductance in a System-on-Chip (SoC) environment also can be neglected if the on-chip inductance is conservativly estimated.