Articles | Volume 8
Adv. Radio Sci., 8, 289–294, 2010
https://doi.org/10.5194/ars-8-289-2010
Adv. Radio Sci., 8, 289–294, 2010
https://doi.org/10.5194/ars-8-289-2010

  22 Dec 2010

22 Dec 2010

Sparse matrix-vector multiplication on network-on-chip

C.-C. Sun1, J. Götze1, H.-Y. Jheng2, and S.-J. Ruan2 C.-C. Sun et al.
  • 1Dortmund University of Technology, Information Processing Lab, Otto-Hahn-Str. 4, 44227 Dortmund, Germany
  • 2National Taiwan University of Science and Technology, Low-Power System Lab, Taipei 106, Taiwan

Abstract. In this paper, we present an idea for performing matrix-vector multiplication by using Network-on-Chip (NoC) architecture. In traditional IC design on-chip communications have been designed with dedicated point-to-point interconnections. Therefore, regular local data transfer is the major concept of many parallel implementations. However, when dealing with the parallel implementation of sparse matrix-vector multiplication (SMVM), which is the main step of all iterative algorithms for solving systems of linear equation, the required data transfers depend on the sparsity structure of the matrix and can be extremely irregular. Using the NoC architecture makes it possible to deal with arbitrary structure of the data transfers; i.e. with the irregular structure of the sparse matrices. So far, we have already implemented the proposed SMVM-NoC architecture with the size 4×4 and 5×5 in IEEE 754 single float point precision using FPGA.