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Volume 9
ARS, 9, 241–245, 2011
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https://doi.org/10.5194/ars-9-241-2011
© Author(s) 2011. This work is distributed under
the Creative Commons Attribution 3.0 License.
https://doi.org/10.5194/ars-9-241-2011
© Author(s) 2011. This work is distributed under
the Creative Commons Attribution 3.0 License.
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01 Aug 2011
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01 Aug 2011
A low power clock generator with adaptive inter-phase charge balancing for variability compensation in 40-nm CMOS
U. Schulze
,
M. Broich
,
O. Weiss
,
and
T. G. Noll
U. Schulze
×
Chair of Electrical Engineering and Computer Systems, RWTH Aachen University, Germany
M. Broich
×
Chair of Electrical Engineering and Computer Systems, RWTH Aachen University, Germany
O. Weiss
×
Chair of Electrical Engineering and Computer Systems, RWTH Aachen University, Germany
T. G. Noll
×
Chair of Electrical Engineering and Computer Systems, RWTH Aachen University, Germany
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