A sensing circuit for single-ended read-ports of SRAM cells with bit-line power reduction and access-time enhancement

Heselhaus, T.; Noll, T. G.

doi:https://doi.org/10.5194/ars-9-247-2011

Articles | Volume 9

https://doi.org/10.5194/ars-9-247-2011

© Author(s) 2011. This work is distributed under
the Creative Commons Attribution 3.0 License.

https://doi.org/10.5194/ars-9-247-2011

© Author(s) 2011. This work is distributed under
the Creative Commons Attribution 3.0 License.

Articles | Volume 9

01 Aug 2011

| 01 Aug 2011

A sensing circuit for single-ended read-ports of SRAM cells with bit-line power reduction and access-time enhancement

T. Heselhaus and T. G. Noll

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Total article views: 2,264 (including HTML, PDF, and XML)

HTML	PDF	XML	Total	BibTeX	EndNote
747	1,393	124	2,264	141	126

HTML: 747
PDF: 1,393
XML: 124
Total: 2,264
BibTeX: 141
EndNote: 126

Views and downloads (calculated since 01 Feb 2013)

Month	HTML	PDF	XML	Total
Feb 2013	3	24	2	29
Mar 2013	3	29	3	35
Apr 2013	4	38	0	42
May 2013	3	26	1	30
Jun 2013	1	16	0	17
Jul 2013	4	21	0	25
Aug 2013	13	0	13
Sep 2013	7	36	1	44
Oct 2013	1	18	0	19
Nov 2013	3	27	0	30
Dec 2013	3	42	3	48
Jan 2014	5	37	2	44
Feb 2014	5	33	2	40
Mar 2014	2	41	0	43
Apr 2014	6	21	0	27
May 2014	1	22	1	24
Jun 2014	13	0	13
Jul 2014	4	30	2	36
Aug 2014	3	29	0	32
Sep 2014	1	35	0	36
Oct 2014	5	19	0	24
Nov 2014	3	23	1	27
Dec 2014	6	20	3	29
Jan 2015	1	8	0	9
Feb 2015	9	6	1	16
Mar 2015	8	9	0	17
Apr 2015	10	7	0	17
May 2015	4	12	1	17
Jun 2015	21	6	0	27
Jul 2015	13	14	0	27
Aug 2015	4	8	0	12
Sep 2015	5	13	1	19
Oct 2015	8	8	0	16
Nov 2015	12	18	0	30
Dec 2015	4	11	0	15
Jan 2016	14	12	1	27
Feb 2016	9	22	2	33
Mar 2016	10	13	0	23
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May 2016	6	15	1	22
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May 2018	8	8	3	19
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Jan 2019	9	5	0	14
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May 2019	8	6	1	15
Jun 2019	3	8	0	11
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Aug 2019	3	5	0	8
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Nov 2019	2	12	0	14
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Feb 2025	9	2	0	11
Mar 2025	7	5	0	12
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Cumulative views and downloads (calculated since 01 Feb 2013)

Month	HTML	PDF	XML	Total
Feb 2013	3	24	2	29
Mar 2013	3	29	3	35
Apr 2013	4	38	0	42
May 2013	3	26	1	30
Jun 2013	1	16	0	17
Jul 2013	4	21	0	25
Aug 2013	13	0	13
Sep 2013	7	36	1	44
Oct 2013	1	18	0	19
Nov 2013	3	27	0	30
Dec 2013	3	42	3	48
Jan 2014	5	37	2	44
Feb 2014	5	33	2	40
Mar 2014	2	41	0	43
Apr 2014	6	21	0	27
May 2014	1	22	1	24
Jun 2014	13	0	13
Jul 2014	4	30	2	36
Aug 2014	3	29	0	32
Sep 2014	1	35	0	36
Oct 2014	5	19	0	24
Nov 2014	3	23	1	27
Dec 2014	6	20	3	29
Jan 2015	1	8	0	9
Feb 2015	9	6	1	16
Mar 2015	8	9	0	17
Apr 2015	10	7	0	17
May 2015	4	12	1	17
Jun 2015	21	6	0	27
Jul 2015	13	14	0	27
Aug 2015	4	8	0	12
Sep 2015	5	13	1	19
Oct 2015	8	8	0	16
Nov 2015	12	18	0	30
Dec 2015	4	11	0	15
Jan 2016	14	12	1	27
Feb 2016	9	22	2	33
Mar 2016	10	13	0	23
Apr 2016	7	10	0	17
May 2016	6	15	1	22
Jun 2016	4	1	0	5
Jul 2016	6	4	1	11
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Apr 2017	8	15	0	23
May 2017	13	20	1	34
Jun 2017	9	20	0	29
Jul 2017	9	12	2	23
Aug 2017	3	7	0	10
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Oct 2017	14	0	14
Nov 2017	6	10	0	16
Dec 2017	7	8	2	17
Jan 2018	2	10	0	12
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Apr 2018	6	8	2	16
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May 2019	8	6	1	15
Jun 2019	3	8	0	11
Jul 2019	2	2	0	4
Aug 2019	3	5	0	8
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Oct 2019	3	4	2	9
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May 2020	2	7	1	10
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Jul 2020	41	33	36	110
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Nov 2021	7	12	0	19
Dec 2021	6	5	0	11
Jan 2022	4	5	0	9
Feb 2022	3	2	1	6
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May 2022	5	2	1	8
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Jul 2022	4	2	0	6
Aug 2022	2	3	0	5
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Oct 2022	3	5	0	8
Nov 2022	2	5	0	7
Dec 2022	3	7	0	10
Jan 2023	4	5	0	9
Feb 2023	1	3	0	4
Mar 2023	4	1	5
Apr 2023	2	0	2
May 2023	4	2	0	6
Jun 2023	3	2	0	5
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Jan 2025	1	3	0	4
Feb 2025	9	2	0	11
Mar 2025	7	5	0	12
Apr 2025	7	2	1	10
May 2025	8	2	2	12
Jun 2025	1	0	1

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Latest update: 03 Jun 2025

A sensing circuit for single-ended read-ports of SRAM cells with bit-line power reduction and access-time enhancement

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