A sensing circuit for single-ended read-ports of SRAM cells with bit-line power reduction and access-time enhancement

Heselhaus, T.; Noll, T. G.

doi:https://doi.org/10.5194/ars-9-247-2011

Articles | Volume 9

https://doi.org/10.5194/ars-9-247-2011

© Author(s) 2011. This work is distributed under
the Creative Commons Attribution 3.0 License.

https://doi.org/10.5194/ars-9-247-2011

© Author(s) 2011. This work is distributed under
the Creative Commons Attribution 3.0 License.

Articles | Volume 9

01 Aug 2011

| 01 Aug 2011

A sensing circuit for single-ended read-ports of SRAM cells with bit-line power reduction and access-time enhancement

T. Heselhaus and T. G. Noll

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Total article views: 2,216 (including HTML, PDF, and XML)

HTML	PDF	XML	Total	BibTeX	EndNote
715	1,380	121	2,216	120	114

HTML: 715
PDF: 1,380
XML: 121
Total: 2,216
BibTeX: 120
EndNote: 114

Views and downloads (calculated since 01 Feb 2013)

Month	HTML	PDF	XML	Total
Feb 2013	3	24	2	29
Mar 2013	3	29	3	35
Apr 2013	4	38	0	42
May 2013	3	26	1	30
Jun 2013	1	16	0	17
Jul 2013	4	21	0	25
Aug 2013	13	0	13
Sep 2013	7	36	1	44
Oct 2013	1	18	0	19
Nov 2013	3	27	0	30
Dec 2013	3	42	3	48
Jan 2014	5	37	2	44
Feb 2014	5	33	2	40
Mar 2014	2	41	0	43
Apr 2014	6	21	0	27
May 2014	1	22	1	24
Jun 2014	13	0	13
Jul 2014	4	30	2	36
Aug 2014	3	29	0	32
Sep 2014	1	35	0	36
Oct 2014	5	19	0	24
Nov 2014	3	23	1	27
Dec 2014	6	20	3	29
Jan 2015	1	8	0	9
Feb 2015	9	6	1	16
Mar 2015	8	9	0	17
Apr 2015	10	7	0	17
May 2015	4	12	1	17
Jun 2015	21	6	0	27
Jul 2015	13	14	0	27
Aug 2015	4	8	0	12
Sep 2015	5	13	1	19
Oct 2015	8	8	0	16
Nov 2015	12	18	0	30
Dec 2015	4	11	0	15
Jan 2016	14	12	1	27
Feb 2016	9	22	2	33
Mar 2016	10	13	0	23
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May 2016	6	15	1	22
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Apr 2017	8	15	0	23
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Jan 2018	2	10	0	12
Feb 2018	2	2	1	5
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Apr 2018	6	8	2	16
May 2018	8	8	3	19
Jun 2018	3	4	1	8
Jul 2018	4	8	1	13
Aug 2018	9	7	1	17
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Jan 2019	9	5	0	14
Feb 2019	11	3	1	15
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Apr 2019	7	6	1	14
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Jun 2019	3	8	0	11
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Jul 2020	41	33	36	110
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May 2023	4	2	0	6
Jun 2023	3	2	0	5
Jul 2023	1	1	0	2
Aug 2023	1	2	0	3
Sep 2023	1	4	1	6
Oct 2023	1	0	1
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Mar 2024	1	2	0	3
Apr 2024	3	2	2	7
May 2024	6	1	4	11
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Jul 2024	12	8	3	23
Aug 2024	4	1	2	7
Sep 2024	3	3	2	8
Oct 2024	4	3	1	8
Nov 2024	2	2	0	4
Dec 2024	1	4	1	6
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Cumulative views and downloads (calculated since 01 Feb 2013)

Month	HTML	PDF	XML	Total
Feb 2013	3	24	2	29
Mar 2013	3	29	3	35
Apr 2013	4	38	0	42
May 2013	3	26	1	30
Jun 2013	1	16	0	17
Jul 2013	4	21	0	25
Aug 2013	13	0	13
Sep 2013	7	36	1	44
Oct 2013	1	18	0	19
Nov 2013	3	27	0	30
Dec 2013	3	42	3	48
Jan 2014	5	37	2	44
Feb 2014	5	33	2	40
Mar 2014	2	41	0	43
Apr 2014	6	21	0	27
May 2014	1	22	1	24
Jun 2014	13	0	13
Jul 2014	4	30	2	36
Aug 2014	3	29	0	32
Sep 2014	1	35	0	36
Oct 2014	5	19	0	24
Nov 2014	3	23	1	27
Dec 2014	6	20	3	29
Jan 2015	1	8	0	9
Feb 2015	9	6	1	16
Mar 2015	8	9	0	17
Apr 2015	10	7	0	17
May 2015	4	12	1	17
Jun 2015	21	6	0	27
Jul 2015	13	14	0	27
Aug 2015	4	8	0	12
Sep 2015	5	13	1	19
Oct 2015	8	8	0	16
Nov 2015	12	18	0	30
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Feb 2016	9	22	2	33
Mar 2016	10	13	0	23
Apr 2016	7	10	0	17
May 2016	6	15	1	22
Jun 2016	4	1	0	5
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Apr 2017	8	15	0	23
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Oct 2017	14	0	14
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Jul 2022	4	2	0	6
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Jan 2023	4	5	0	9
Feb 2023	1	3	0	4
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Apr 2023	2	0	2
May 2023	4	2	0	6
Jun 2023	3	2	0	5
Jul 2023	1	1	0	2
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Oct 2023	1	0	1
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Mar 2024	1	2	0	3
Apr 2024	3	2	2	7
May 2024	6	1	4	11
Jun 2024	6	2	2	10
Jul 2024	12	8	3	23
Aug 2024	4	1	2	7
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Oct 2024	4	3	1	8
Nov 2024	2	2	0	4
Dec 2024	1	4	1	6
Jan 2025	1	1	0	2

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Latest update: 22 Jan 2025

A sensing circuit for single-ended read-ports of SRAM cells with bit-line power reduction and access-time enhancement

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