A sensing circuit for single-ended read-ports of SRAM cells with bit-line power reduction and access-time enhancement

Heselhaus, T.; Noll, T. G.

doi:https://doi.org/10.5194/ars-9-247-2011

Articles | Volume 9

https://doi.org/10.5194/ars-9-247-2011

© Author(s) 2011. This work is distributed under
the Creative Commons Attribution 3.0 License.

https://doi.org/10.5194/ars-9-247-2011

© Author(s) 2011. This work is distributed under
the Creative Commons Attribution 3.0 License.

Articles | Volume 9

01 Aug 2011

| 01 Aug 2011

A sensing circuit for single-ended read-ports of SRAM cells with bit-line power reduction and access-time enhancement

T. Heselhaus and T. G. Noll

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Total article views: 2,134 (including HTML, PDF, and XML)

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673	1,355	106	2,134	106	102

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PDF: 1,355
XML: 106
Total: 2,134
BibTeX: 106
EndNote: 102

Views and downloads (calculated since 01 Feb 2013)

Month	HTML	PDF	XML	Total
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Mar 2013	3	29	3	35
Apr 2013	4	38	0	42
May 2013	3	26	1	30
Jun 2013	1	16	0	17
Jul 2013	4	21	0	25
Aug 2013	13	0	13
Sep 2013	7	36	1	44
Oct 2013	1	18	0	19
Nov 2013	3	27	0	30
Dec 2013	3	42	3	48
Jan 2014	5	37	2	44
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Apr 2014	6	21	0	27
May 2014	1	22	1	24
Jun 2014	13	0	13
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Aug 2014	3	29	0	32
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Jan 2015	1	8	0	9
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Jan 2016	14	12	1	27
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Cumulative views and downloads (calculated since 01 Feb 2013)

Month	HTML	PDF	XML	Total
Feb 2013	3	24	2	29
Mar 2013	3	29	3	35
Apr 2013	4	38	0	42
May 2013	3	26	1	30
Jun 2013	1	16	0	17
Jul 2013	4	21	0	25
Aug 2013	13	0	13
Sep 2013	7	36	1	44
Oct 2013	1	18	0	19
Nov 2013	3	27	0	30
Dec 2013	3	42	3	48
Jan 2014	5	37	2	44
Feb 2014	5	33	2	40
Mar 2014	2	41	0	43
Apr 2014	6	21	0	27
May 2014	1	22	1	24
Jun 2014	13	0	13
Jul 2014	4	30	2	36
Aug 2014	3	29	0	32
Sep 2014	1	35	0	36
Oct 2014	5	19	0	24
Nov 2014	3	23	1	27
Dec 2014	6	20	3	29
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Jan 2024	1	0	1
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Latest update: 28 Apr 2024

A sensing circuit for single-ended read-ports of SRAM cells with bit-line power reduction and access-time enhancement

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