FPGA implementation of trellis decoders for linear block codes
- 1Microelectronic Systems Design Research Group, University of Kaiserslautern, 67663 Kaiserslautern, Germany
- 2Institute of Informatics, Federal University of Rio Grande do Sul, 91501970 Porto Alegre, Brazil
Abstract. Forward error correction based on trellises has been widely adopted for convolutional codes. Because of their efficiency, they have also gained a lot of interest from a theoretic and algorithm point of view for the decoding of block codes. In this paper we present for the first time hardware architectures and implementations for trellis decoding of block codes. A key feature is the use of a sophisticated permutation network, the Banyan network, to implement the time varying structure of the trellis. We have implemented the Viterbi and the max-log-MAP algorithm in different folded versions on a Xilinx Virtex 6 FPGA.