Articles | Volume 12
https://doi.org/10.5194/ars-12-61-2014
https://doi.org/10.5194/ars-12-61-2014
10 Nov 2014
 | 10 Nov 2014

FPGA implementation of trellis decoders for linear block codes

S. Scholl, E. Leonardi, and N. Wehn

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Cited articles

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Goke, L. R. and Lipovski, G. J.: Banyan Networks for Partitioning Multiprocessor Systems, 1st Annual Symposium on Computer Architecture, 21–28, 1973.
Hekstra, A. P.: An Alternative to Metric Rescaling in Viterbi Decoders, IEEE T. Commun., 37, 1220–1222, 1989.
Kim, S., Ryoo, S., and Lee, S.: Block Turbo Codes Using Multiple Soft Outputs, in: Proceedings of the 3rd ISTC, Vol. 1, 247–250, Brest, 2003.