11 citations as recorded by crossref.

1. Design of a reversible single precision floating point subtractor A. Anantha Lakshmi & G. Sudha https://doi.org/10.1186/2193-1801-3-11
2. Power Efficient Technique for CMOS- Logic Circuits M. Adhikari et al. https://doi.org/10.1088/1742-6596/2327/1/012015
3. Improving the energy efficiency of reversible logic circuits by the combined use of adiabatic styles M. Khatir et al. https://doi.org/10.1016/j.vlsi.2010.09.004
4. A novel power efficient 0.64-GFlops fused 32-bit reversible floating point arithmetic unit architecture for digital signal processing applications A. AnanthaLakshmi & G. Sudha https://doi.org/10.1016/j.micpro.2017.01.002
5. Leakage Reduction of P-Type Logic Circuits Using Pass-Transistor Adiabatic Logic with PMOS Pull-up Configuration J. Jiang et al. https://doi.org/10.4028/www.scientific.net/AMM.39.73
6. A comprehensive analysis on the resilience of adiabatic logic families against transient faults R. Narimani et al. https://doi.org/10.1016/j.vlsi.2020.01.004
7. Low‐power adiabatic 9T static random access memory Y. Takahashi et al. https://doi.org/10.1049/joe.2014.0009
8. Energy Conservation of Adiabatic ECRL-Based Kogge-Stone Adder Circuits for FFT Applications P. Dhilipkumar & G. Mohanbabu https://doi.org/10.32604/iasc.2022.021663
9. Evolutionary Approach of Adiabatic Logic Design on Low Power Solution �A Robust Survey A. Kumar et al. https://doi.org/10.26634/jcs.1.2.1775
10. RELIABILITY ANALYSIS OF FinFET-BASED ADIABATIC LOGIC STRUCTURES S. Kaza et al. https://doi.org/10.1615/TelecomRadEng.2025053982
11. Optimizing CMOS Circuits for Performance Improvements Using Adiabatic Logic P. Vijayakuma et al. https://doi.org/10.3923/itj.2007.325.331