Implementation and modeling of parametrizable high-speed Reed Solomon decoders on FPGAs

Flocke, A.; Blume, H.; Noll, T. G.

doi:https://doi.org/10.5194/ars-3-271-2005

Articles | Volume 3

https://doi.org/10.5194/ars-3-271-2005

© Author(s) 2005. This work is licensed under
the Creative Commons Attribution-NonCommercial-ShareAlike 2.5 License.

https://doi.org/10.5194/ars-3-271-2005

© Author(s) 2005. This work is licensed under
the Creative Commons Attribution-NonCommercial-ShareAlike 2.5 License.

Articles | Volume 3

12 May 2005

| 12 May 2005

Implementation and modeling of parametrizable high-speed Reed Solomon decoders on FPGAs

A. Flocke, H. Blume, and T. G. Noll

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Total article views: 1,313 (including HTML, PDF, and XML)

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Views and downloads (calculated since 01 Feb 2013)

Month	HTML	PDF	XML	Total
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Mar 2013	3	8	3	14
Apr 2013	1	4	0	5
May 2013	1	5	1	7
Jun 2013	1	6	0	7
Jul 2013	3	7	0	10
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Nov 2013	7	0	7
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Aug 2014	6	0	6
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Jan 2015	9	0	9
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Feb 2016	7	6	1	14
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Jan 2024	1	0	1
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Feb 2013	1	5	1	7
Mar 2013	3	8	3	14
Apr 2013	1	4	0	5
May 2013	1	5	1	7
Jun 2013	1	6	0	7
Jul 2013	3	7	0	10
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Sep 2013	3	9	1	13
Oct 2013	1	5	0	6
Nov 2013	7	0	7
Dec 2013	3	8	2	13
Jan 2014	2	7	2	11
Feb 2014	4	10	3	17
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Apr 2014	4	7	0	11
May 2014	3	7	2	12
Jun 2014	1	8	0	9
Jul 2014	4	9	2	15
Aug 2014	6	0	6
Sep 2014	8	0	8
Oct 2014	3	10	0	13
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Dec 2014	8	10	2	20
Jan 2015	9	0	9
Feb 2015	5	3	1	9
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Jan 2024	1	0	1
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Mar 2024	2	6	1	9
Apr 2024	3	2	2	7

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Implementation and modeling of parametrizable high-speed Reed Solomon decoders on FPGAs

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