Implementation and modeling of parametrizable high-speed Reed Solomon decoders on FPGAs

Flocke, A.; Blume, H.; Noll, T. G.

doi:https://doi.org/10.5194/ars-3-271-2005

Articles | Volume 3

https://doi.org/10.5194/ars-3-271-2005

© Author(s) 2005. This work is licensed under
the Creative Commons Attribution-NonCommercial-ShareAlike 2.5 License.

https://doi.org/10.5194/ars-3-271-2005

© Author(s) 2005. This work is licensed under
the Creative Commons Attribution-NonCommercial-ShareAlike 2.5 License.

Articles | Volume 3

12 May 2005

| 12 May 2005

Implementation and modeling of parametrizable high-speed Reed Solomon decoders on FPGAs

A. Flocke, H. Blume, and T. G. Noll

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Total article views: 1,344 (including HTML, PDF, and XML)

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EndNote: 100

Views and downloads (calculated since 01 Feb 2013)

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Mar 2013	3	8	3	14
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Jun 2013	1	6	0	7
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Implementation and modeling of parametrizable high-speed Reed Solomon decoders on FPGAs

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