Articles | Volume 15
https://doi.org/10.5194/ars-15-157-2017
https://doi.org/10.5194/ars-15-157-2017
21 Sep 2017
 | 21 Sep 2017

Channel Analysis for a 6.4 Gb s−1 DDR5 Data Buffer Receiver Front-End

Stefanie Lehmann and Friedel Gerfers

Viewed

Total article views: 2,751 (including HTML, PDF, and XML)
HTML PDF XML Total BibTeX EndNote
830 1,821 100 2,751 101 100
  • HTML: 830
  • PDF: 1,821
  • XML: 100
  • Total: 2,751
  • BibTeX: 101
  • EndNote: 100
Views and downloads (calculated since 21 Sep 2017)
Cumulative views and downloads (calculated since 21 Sep 2017)

Viewed (geographical distribution)

Total article views: 2,567 (including HTML, PDF, and XML) Thereof 2,563 with geography defined and 4 with unknown origin.
Country # Views %
  • 1
1
 
 
 
 
Latest update: 08 Jun 2025
Download
Short summary
The next generation DDR5 memory operates at double the frequency of DDR4 memory. At 6.4 Gbit s−1 per port, the transmitted symbols are severely distorted at the receiver. Equalisation can be used to partly recover the distorted signal. In this work, a back-plane channel is analysed to derive the requirements for receiver-side equalisation. Based on these results, different correction methods for DDR5 data buffer front-ends are discussed. The results of the equalisation are shown.
Share