Advances in Radio Science
Advances in Radio Science
ARS
Articles | Volume 15
Articles | Volume 15
https://doi.org/10.5194/ars-15-157-2017
© Author(s) 2017. This work is distributed under
the Creative Commons Attribution 3.0 License.
https://doi.org/10.5194/ars-15-157-2017
© Author(s) 2017. This work is distributed under
the Creative Commons Attribution 3.0 License.
Articles | Volume 15
21 Sep 2017
 | 21 Sep 2017

Channel Analysis for a 6.4 Gb s−1 DDR5 Data Buffer Receiver Front-End

Stefanie Lehmann and Friedel Gerfers

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Short summary
The next generation DDR5 memory operates at double the frequency of DDR4 memory. At 6.4 Gbit s−1 per port, the transmitted symbols are severely distorted at the receiver. Equalisation can be used to partly recover the distorted signal. In this work, a back-plane channel is analysed to derive the requirements for receiver-side equalisation. Based on these results, different correction methods for DDR5 data buffer front-ends are discussed. The results of the equalisation are shown.
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