Articles | Volume 15
https://doi.org/10.5194/ars-15-157-2017
https://doi.org/10.5194/ars-15-157-2017
21 Sep 2017
 | 21 Sep 2017

Channel Analysis for a 6.4 Gb s−1 DDR5 Data Buffer Receiver Front-End

Stefanie Lehmann and Friedel Gerfers

Related authors

Advanced design and characterization methodologies for memory-aware CMOS power-amplifier implementation
Martin Schleyer, Dominic Maurath, Heinrich Klar, and Friedel Gerfers
Adv. Radio Sci., 15, 49–54, https://doi.org/10.5194/ars-15-49-2017,https://doi.org/10.5194/ars-15-49-2017, 2017
Short summary

Cited articles

Agrawal, A., Bulzacchelli, J., Dickson, T., Liu, Y., Tierno, J., and Friedman, D.: A 19 Gb/s serial link receiver with both 4-tap FFE and 5-tap DFE functions in 45 nm SOI CMOS, in: Proc. IEEE Int. Solid-State Circuits Conf., 19–23 February 2012, San Francisco, USA, 134–136, https://doi.org/10.1109/ISSCC.2012.6176951, 2012.
Balamurugan, G., Casper, B., Jaussi, J. E., Mansuri, M., O'Mahony, F., and Kennedy, J.: Modeling and Analysis of High-Speed I/O Links, IEEE T. Adv. Packaging, 32, 237–247, https://doi.org/10.1109/TADVP.2008.2011366, 2009.
JEDEC Solid State Technology Association: DDR4 SDRAM Load Reduced DIMM Design Specification, available at: https://www.jedec.org (last access: 24 May 2017), 2015.
Liu, J. and Lin, X.: Equalization in high-speed communication systems, IEEE Circ. Syst. Mag., 4, 4–17, https://doi.org/10.1109/MCAS.2004.1330746, 2004.
Download
Short summary
The next generation DDR5 memory operates at double the frequency of DDR4 memory. At 6.4 Gbit s−1 per port, the transmitted symbols are severely distorted at the receiver. Equalisation can be used to partly recover the distorted signal. In this work, a back-plane channel is analysed to derive the requirements for receiver-side equalisation. Based on these results, different correction methods for DDR5 data buffer front-ends are discussed. The results of the equalisation are shown.