Advanced design and characterization methodologies for memory-aware CMOS power-amplifier implementation

Abstract. This paper reports on an effective root-cause analysis method of memory effects in power amplifiers, as well as introduces compensation techniques on a circuit design level. Despite conventional memory-effect approaches, the discussed method uses a two-tone scan over a wide operation and modulation range. This enables an in-depth study of physical causes and helps to implement compensation techniques at design stage. On the one hand, this circuit investigation is optimized using an automated SystemC model parametrized with real device and measurement values. Hence, computation time is widely reduced which shortens design cycles. On the other hand, the implementation of the derived circuit compensation means will reduce the complexity of digital pre-distortion due to a reduced memory-effect induced AM/AM and AM/PM hysteresis. The approach is demonstrated on a 65 nm CMOS power amplifier with an OIP1 of 27 dBm and a PAE of over 30 % using WCDMA and LTE signals. In fact, mismatch could be reduced by more than 8 %.