Articles | Volume 16
Adv. Radio Sci., 16, 99–108, 2018
Adv. Radio Sci., 16, 99–108, 2018

  04 Sep 2018

04 Sep 2018

High-Speed Serializer for a 64 GS s−1 Digital-to-Analog Converter in a 28 nm Fully-Depleted Silicon-on-Insulator CMOS Technology

Daniel Widmann et al.

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Cited articles

Cao, J., Cui, D., Nazemi, A., He, T., Li, G., Catli, B., Khanpour, M., Hu, K., Ali, T., Zhang, H., Yu, H., Rhew, B., Sheng, S., Shim, Y., Zhang, B., and Momtaz, A.: A transmitter and receiver for 100Gb/s coherent networks with integrated 4x64GS/s 8b ADCs and DACs in 20nm CMOS, in: 2017 IEEE International Solid-State Circuits Conference (ISSCC), 484–485, 2017. a, b, c, d
Chao, S. F., Kuo, J. J., Lin, C. L., Tsai, M. D., and Wang, H.: A DC-11.5 GHz Low-Power, Wideband Amplifier Using Splitting-Load Inductive Peaking Technique, IEEE Microw. Wirel. Co., 18, 482–484, 2008. a
Greshishchev, Y. M., Pollex, D., Wang, S. C., Besson, M., Flemeke, P., Szilagyi, S., Aguirre, J., Falt, C., Ben-Hamida, N., Gibbins, R., and Schvan, P.: A 56GS/S 6b DAC in 65nm CMOS with 256x6b memory, in: 2011 IEEE International Solid-State Circuits Conference, 194–196, 2011. a
Huang, H., Heilmeyer, J., Grözing, M., and Berroth, M.: An 8-bit 100-GS/s distributed DAC in 28-nm CMOS, IEEE Rad. Freq. Integr., 65–68, 2014. a
Huang, H., Heilmeyer, J., Grözing, M., Berroth, M., Leibrich, J., and Rosenkranz, W.: An 8-bit 100-GS/s Distributed DAC in 28-nm CMOS for Optical Communications, IEEE T. Microw. Theory, 63, 1211–1218, 2015. a, b
Short summary
Digital-to-analog converters (DACs) with very high conversion rates and bandwidth are of special interest for optical coherent transceiver systems and arbitrary waveform generators. An attractive solution to provide several channels with very high data rates of tens of Gbit/s is to use a high speed serializer. We present a CMOS serializer consisting of a 19 channel 16:1 multiplexer (MUX) for output data rates up to 64 Gbit/s per channel and a low skew clock distribution network.