Charge pump design in 130 nm SiGe BiCMOS technology for low-noise fractional-N PLLs

Kucharski, M.; Herzel, F.

doi:10.5194/ars-13-133-2015

Articles | Volume 13

https://doi.org/10.5194/ars-13-133-2015

© Author(s) 2015. This work is distributed under
the Creative Commons Attribution 3.0 License.

https://doi.org/10.5194/ars-13-133-2015

© Author(s) 2015. This work is distributed under
the Creative Commons Attribution 3.0 License.

Articles | Volume 13

03 Nov 2015

| 03 Nov 2015

Charge pump design in 130 nm SiGe BiCMOS technology for low-noise fractional-N PLLs

M. Kucharski and F. Herzel

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Latest update: 19 Apr 2026

Short summary

This paper presents a charge pump (CP) designed for a high linearity and a low noise to be used in a fractional-N phase-locked loop (PLL). An internal supply regulator with low intrinsic device noise is included in the design optimization. The high CP linearity is shown to reduce the level of in-band spurs in a fractional-N PLL tremendously.