Articles | Volume 13
https://doi.org/10.5194/ars-13-133-2015
https://doi.org/10.5194/ars-13-133-2015
03 Nov 2015
 | 03 Nov 2015

Charge pump design in 130 nm SiGe BiCMOS technology for low-noise fractional-N PLLs

M. Kucharski and F. Herzel

Cited articles

Arora, H., Klemmer, N., Morizio, J. C., and Wolf, P. D.: Enhanced phase noise modeling of fractional-N frequency synthesizers, IEEE T. Circuits S-I, 52, 379–395, 2005.
Brokaw, A. P.: A simple three-terminal IC bandgap reference, IEEE J. Solid-St. Circ., 9, 388–393, 1974.
Chien, H.-M., Lin, T.-H., Ibrahim, B., Zhang, L., Rofougaran, M., Rofougaran, A., and Kaiser, W. J.: A 4 GHz fractional-N synthesizer for IEEE 802.11a, in: 2004 Symposium on VLSI Circuits Digest of Technical Papers, Honolulu, USA, 46–49, 2004.
De Muer, B. and Steyaert, M. S. J.: On the analysis of Δ σ fractional-N frequency synthesizers, IEEE T. Circuits S-II, 50, 784–793, 2003.
Hedayati, H. and Bakkaloglu, B.: A 3 GHz wideband σΔ fractional-N synthesizer with voltage-mode exponential CP-PFD, in: Proc. of 2009 IEEE Radio Frequency Integrated Circuits Symposium (RFIC 2009), Boston, USA, June 2009, 325–328, 2009.
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Short summary
This paper presents a charge pump (CP) designed for a high linearity and a low noise to be used in a fractional-N phase-locked loop (PLL). An internal supply regulator with low intrinsic device noise is included in the design optimization. The high CP linearity is shown to reduce the level of in-band spurs in a fractional-N PLL tremendously.